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MC10E445, MC100E445 5V ECL 4-Bit Serial/Parallel Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to http://onsemi.com 2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1 etc. PLCC-28 FN SUFFIX Two selectable serial inputs provide a loopback capability for testing CASE 776 purposes when the device is used in conjunction with the E446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse applied asynchronously for at least two input clock cycles MARKING DIAGRAM* shifts the start bit for conversion from Qn to Qn-1. For each additional 1 28 shift required an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to "swallow" a clock pulse, effectively shifting a bit from the Qn to the Qn-1 output (see Timing Diagram B). MCxxxE445FNG The MODE input is used to select the conversion mode of the device. AWLYYWW With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle thus allowing for an 8-bit conversion xxx = 10 or 100 scheme using two E445's. When cascaded in an 8-bit conversion scheme A = Assembly Location the devices will not operate at the 2.0 Gb/s data rate of a single device. WL = Wafer Lot Refer to the applications section of this data sheet for more information on YY = Year cascading the E445. WW = Work Week Upon power-up the internal flip-flops will attain a random state. To G = Pb-Free Package synchronize multiple E445's in a system the master reset must be asserted. The VBB pin, an internally generated voltage supply, is available to this *For additional marking information, refer to device only. For single-ended input conditions, the unused differential Application Note AND8002/D. input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a ORDERING INFORMATION 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When See detailed ordering and shipping information in the package not used, VBB should be left open. dimensions section on page 11 of this data sheet. The 100 Series contains temperature compensation. Features * ESD Protection: Human Body Model; > 2 kV, * On-Chip Clock /4 and /8 Machine Model; > 100 V * 2.0 Gb/s Data Rate Capability * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Differential Clock and Serial Inputs * Moisture Sensitivity Level: Pb = 1; Pb-Free = 3 * VBB Output for Single-Ended Input Applications For Additional Information, see Application Note * Asynchronous Data Synchronization AND8003/D * Mode Select to Expand to 8-Bits * Flammability Rating: UL 94 V-0 @ 0.125 in, * PECL Mode Operating Range: VCC = 4.2 V to 5.7 V Oxygen Index: 28 to 34 with VEE = 0 V * Transistor Count = 528 devices * NECL Mode Operating Range: VCC = 0 V * PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = -4.2 V to -5.7 V with VEE = 0 V * Internal Input 50 kW Pulldown Resistors * Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 12
1
Publication Order Number: MC10E445/D
MC10E445, MC100E445
RESET SYNC
Table 1. PIN DESCRIPTION
MODE NC VCCO 21 20 19 18 17 16 SOUT SOUT VCC Q0 Q1 VCCO Q2 PIN SINA, SINA SINB, SINB SEL Q0-Q3 CLK, CLK CL/4, CL/4 CL/8, CL/8 MODE SYNCH VBB VCC, VCCO VEE NC FUNCTION ECL Differential Serial Data Input A ECL Differential Serial Data Input B ECL Serial Input Selector Pin ECL Parallel Data Outputs ECL Differential Clock Inputs ECL Differential /4 Clock Output ECL Differential /8 Clock Output ECL Conversion Mode 4-Bit/8-Bit ECL Conversion Synchronizing Input Reference Voltage Output Positive Supply Negative Supply No Connect
SINA SINA SINB SINB SEL VEE CLK CLK VBB 26 27 28 1 2 3 4 5 6 25 24
23
22
MC10E445
15 14 13 12
7
8
9
10
11
CL/8 CL/8 VCCO CL/4 CL/4 VCCO Q3 * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC-28 (Top View)
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MC10E445, MC100E445
SINB SINB SINA SINA SEL D Q D Q Q2 D Q D Q Q3
D
Q
D
Q
Q1
D
Q
D
Q
Q0
SOUT SOUT 1 0 MODE Out /4 R CL/4 CL/4
CLK CLK
In Out Latch EN
SYNC
D
Q
D Q
Out /2 R
CL/8 CL/8
VBB
RESET
Figure 2. Logic Diagram Table 2. FUNCTION TABLES
Mode L H Conversion 4-Bit 8-Bit SEL H L Serial Input A B
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MC10E445, MC100E445
Table 3. MAXIMUM RATINGS
Symbol VCC VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board PLCC-28 PLCC-28 PLCC-28 Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 6 -6 50 100 0.5 0 to +85 -65 to +150 63.5 43.5 22 to 26 265 265 Unit V V V mA mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC10E445, MC100E445
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0C Symbol IEE VOH VOHsout VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output HIGH Voltage sout/sout Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) Input HIGH Current Input LOW Current 0.5 0.3 3980 3975 3050 3830 3050 3.62 2.2 3210 3995 3285 Min Typ 154 4070 Max 185 4160 4170 3370 4160 3520 3.74 4.6 4020 3975 3050 3870 3050 3.65 2.2 3210 4030 3285 Min 25C Typ 154 4105 Max 185 4190 4170 3370 4190 3520 3.75 4.6 4090 3975 3050 3940 3050 3.69 2.2 3227 4110 3302 Min 85C Typ 154 4185 Max 185 4280 4170 3405 4280 3555 3.81 4.6 Unit mA mV mV mV mV mV V V
IIH IIL
150 0.5 0.25
150 0.3 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = -5.0 V (Note 4)
0C Symbol IEE VOH VOHsout VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output HIGH Voltage sout/sout Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Input HIGH Current Input LOW Current 0.5 0.3 -1020 -1025 -1950 -1170 -1950 -1.38 -2.8 -1790 -1005 -1715 Min Typ 154 -930 Max 185 -840 -830 -1630 -840 -1480 -1.27 -0.4 -980 -1025 -1950 -1130 -1950 -1.35 -2.8 -1790 -970 -1715 Min 25C Typ 154 -895 Max 185 -810 -830 -1630 -810 -1480 -1.25 -0.4 -910 -1025 -1950 -1060 -1950 -1.31 -2.8 -1773 -970 -1698 Min 85C Typ 154 -815 Max 185 -720 -830 -1595 -720 -1445 -1.19 -0.4 Unit mA mV mV mV mV mV V V
IIH IIL
150 0.5 0.065
150 0.3 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E445, MC100E445
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)
0C Symbol IEE VOH VOHsout VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output HIGH Voltage sout/sout Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration Configuration) (Note 9) Input HIGH Current Input LOW Current 0.5 0.3 3975 3975 3190 3835 3190 3.62 2.2 3295 3975 3355 Min Typ 154 4050 Max 185 4120 4170 3380 4120 3525 3.74 4.6 3975 3975 3190 3835 3190 3.62 2.2 3255 3975 3355 Min 25C Typ 154 4050 Max 185 4120 4170 3380 4120 3525 3.74 4.6 3975 3975 3190 3835 3190 3.62 2.2 3260 3975 3355 Min 85C Typ 177 4050 Max 212 4120 4170 3380 4120 3525 3.74 4.6 Unit mA mV mV mV mV mV V V
IIH IIL
150 0.5 0.25
150 0.5 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 8. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = -5.0 V (Note 10)
0C5 Symbol IEE VOH VOHsout VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 11) Output HIGH Voltage sout/sout Output LOW Voltage (Note 11) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) Configuration (Note 12) Input HIGH Current Input LOW Current 0.5 0.3 -1025 -1025 -1810 -1165 -1810 -1.38 -2.8 -1705 -1025 -1645 Min Typ 154 -950 Max 185 -880 -830 -1620 -880 -1475 -1.26 -0.4 -1025 -1025 -1810 -1165 -1810 -1.38 -2.8 -1745 -1025 -1645 Min 25C Typ 154 -950 Max 185 -880 -830 -1620 -880 -1475 -1.26 -0.4 -1025 -1025 -1810 -1165 -1810 -1.38 -2.8 -1740 -1025 -1645 Min 85C Typ 177 -950 Max 212 -880 -830 -1620 -880 -1475 -1.26 -0.4 Unit mA mV mV mV mV mV V V
IIH IIL
150 0.5 0.25
150 0.5 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 11. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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MC10E445, MC100E445
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = -5.0 V (Note 13)
0C Symbol fMAX tPLH tPHL Characteristic Maximum Conversion Frequency Propagation Delay to Output CLK to Q, Reset to Q CLK to SOUT (Diff) CLK to CL/4(Diff) CLK to CL/8(Diff) Setup Time SINA, SINB SEL SINA, SINB, SEL Min 2.0 Typ Max Min 2.0 25C Typ Max Min 2.0 85C Typ Max Unit Gb/s NRZ 1800 975 1325 1325 -250 -200 300 300 2100 1150 1550 1550 ps
1500 800 1100 1100 -100 0 450 500
1800 975 1325 1325 -250 -200 300 300
2100 1150 1550 1550
1500 800 1100 1100 -100 0 450 500 400
1800 975 1325 1325 -250 -200 300 300
2100 1150 1550 1550
1500 800 1100 1100 -100 0 450 500 400
ts
ps
th tRR tPW tJITTER VPP tr tf
Hold Time
ps ps ps
Reset Recovery Time Minimum Pulse Width Random Clock Jitter (RMS) Input Voltage Swing (Differential Configuration) Rise/Fall Times 20%-80% SOUT Other CLK, MR
400 <1 150 1000
<1 150 1000 150
<1 1000
ps mV ps
100 200
225 425
350 650
100 200
225 425
350 650
100 200
225 425
350 650
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. 10 Series: VEE can vary -0.46 V / +0.06 V. 100 Series: VEE can vary -0.46 V / +0.8 V. 14. Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
Reset
tRR
CLK / CLK
Figure 3.
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CLK SIN RESET Q0 Q1 Q2 Q3 SOUT CL/4 CL/8 Dn-4 Dn-3 Dn-4 Dn-3 Dn-2 Dn-1 Dn-2 Dn-1 Dn Dn Dn+1 Dn+2 Dn+3 Dn+1 Dn+2 Dn+3 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3
Timing Diagram A. 1:4 Serial to Parallel Conversion
CLK SIN RESET SYNC Q0 Q1 Q2 Q3 SOUT CL/4 CL/8 Dn-4 Dn-3 Dn-4 Dn-3 Dn-2 Dn-1 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 Dn+1 Dn+2 Dn+3 Dn+4 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4
Timing Diagram B. 1:4 Serial to Parallel Conversion With SYNC Pulse Figure 4. Timing Diagrams
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MC10E445, MC100E445
APPLICATIONS INFORMATION The MC10E/100E445 is an integrated 1:4 serial to parallel converter. The chip is designed to work with the E446 device to provide both transmission and receiving of a high speed serial data path. The E445, can convert up to a 2.0 Gb/s NRZ data stream into 4-bit parallel data. The device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 5 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E445 has an extra buffer delay and thus should be used as the loop back serial input.
PARALLEL DATA SOUT SOUT TO SERIAL MEDIUM CLOCK CLOCK E445a SERIAL INPUT DATA SIN SIN SOUT SOUT SIN SIN Q3 Q2 Q1 Q0 E445b
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4 PARALLEL OUTPUT DATA
Q3 Q2 Q1 Q0
100ps CLOCK Tpd CLK to SOUT 800 ps 1150 ps
PARALLEL DATA
SINA SINA SINB SINB FROM SERIAL MEDIUM
Figure 6. Cascaded 1:8 Converter Architecture
Figure 5. Loopback Test Architecture
The E445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 6 illustrates the architecture for a 1:8 demultiplexer using two E445's; the timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, TPD CLK to SOUT = 1150 ps and tS for SIN = -100 ps, yields a minimum period of 1050 ps or a clock frequency of 950 MHz. The clock frequency is significantly lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445 the frequency of operation can be increased. The delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (Figure 7).
With a minimum delay of 800 ps on this output the clock for the lower order E445 cannot be delayed more than 800 ps relative to the clock of the first E445 without potentially missing a bit of information. Because the setup time on the serial input pin is negative coincident excursions on the data and clock inputs of the E445 will result in correct operation.
CLOCK A
CLOCK B Tpd CLK to SOUT 800 ps 1150 ps
Figure 7. Cascade Frequency Limitation
Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs of the E445. By connecting the clock for the second E445 to the complementary clock input pin the device will clock a half a clock period after the first E445 (Figure 8). Utilizing this simple technique will raise the potential conversion frequency up to 1.4 GHz. The divide by eight clock of the second E445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two E445's will no longer be synchronized. This skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses.
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MC10E445, MC100E445
CLOCK CLOCK E445a SERIAL INPUT DATA SIN SIN SOUT SOUT SIN SIN Q3 Q2 Q1 Q0 E445b 700ps (1.4GHz) CLOCK A CLOCK B Tpd CLK to SOUT 800ps Q7 Q6 Q5 Q4 PARALLEL OUTPUT DATA Q3 Q2 Q1 Q0 1150ps 100ps
Q3 Q2 Q1 Q0
Figure 8. Extended Frequency 1:8 Demultiplexer
CLK SINa Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3
Q0 Q1 Q2 Q3 Q4 (Q0 a) Q5 (Q1 a) Q6 (Q2 a) Q7 (Q3 a) SOUTa SOUTb CL/4a CL/4b CL/8a CL/8b Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn-4 Dn+1 Dn-3
Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+2 Dn-2 Dn+3 Dn-1 Dn Dn+1
Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion
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Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 10. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10E445FN MC10E445FNG MC10E445FNR2 MC10E445FNR2G MC100E445FN MC100E445FNG MC100E445FNR2 MC100E445FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10E445, MC100E445
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10E445, MC100E445
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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